A diode is a critical device in CMOS technology, which can be used in bandgap reference circuits. FIG. 1 shows a conventional CMOS diode formed in a semiconductor substrate 110. The semiconductor substrate 110 comprises a first region 112 that has n-type conductivity and a second region 114 that has p-type conductivity. The first and second regions 112 and 114 jointly define a third region 113 located therebetween in the semiconductor substrate 110, which has either n-type or p-type conductivity, but at a significantly lower dopant concentration in comparison with the first or second regions 112 or 114. The first and second regions 112 and 114 may also comprise surface silicide layers 112A and 114A, as shown in FIG. 1.
The CMOS diode is typically defined by a single gate conductor, which is located over a gate dielectric layer 120 on top of the semiconductor substrate 110 and which includes a first portion 122 of n-type conductivity and a second portion 124 of p-type conductivity, as shown in FIG. 1. The first portion 122 of the gate conductor is located adjacent to the first region 112, and the second portion 124 is located adjacent to the second region 114. The first and second portions 122 and 124 of the gate conductor are in direct contact with each other and are shorted by a common surface silicide layer 123.
One or more optional sidewall spacers 126 may optionally be provided along sidewalls of the gate conductor to isolate the gate conductor from the first and second doped regions 112 and 114. Further, one or more dielectric cap layer 130 can be provided over the entire structure, including the gate conductor as well as the semiconductor substrate 110.
Between the p-doped second region 114 and the n-doped first region 112, a carrier accumulation region 116 is formed in the lightly n-doped third region 113 of the semiconductor substrate 110 and immediately underneath the p-doped second portion 124 of the gate conductor, due to the work function difference between the n-doped and p-doped regions. Further, a depletion region 118 is formed under the carrier accumulation region 116 at the diode interface between the lightly n-doped third region 113 and the p-doped second region 114, as shown in FIG. 1.
The widths of the accumulation region 116 and the depletion region 118 are positively correlated with that of the p-doped second portion 124 of the gate conductor. However, doping of the first and second portions 122 and 124 of the single gate conductor is typically achieved by masked dopant implantation, which, due to limitations of the lithographic tools used, can result in significant overlay mis-alignment and critical dimension (CD) variations. Therefore, the width of the resulting p-doped second portion 124 of the gate conductor may vary significantly. Consequently, the widths of the accumulation region 116 and the depletion region 118 may vary significantly, which in turn leads to deleterious electric field variation at the diode interface.
Performance of the CMOS diode can be measured by a parameter commonly referred to as the diode ideality factor. The diode ideality factor n indicates how closely the I-V (i.e., current-voltage) characteristic of the diode matches the ideal characteristic. For ideal diodes, n=1.0. It is typically desired to have diode ideality variation of less than 0.28% in integrated circuit designs.
However, the width of the accumulation region 116 and its interaction with the underlying depletion region 118 directly impact the diode ideality, because the diode ideality is adversely affected by electron/hole recombination occurred in the depletion region 118, and because the accumulation region 116 provides an source of electrons in addition to the lightly n-doped third region 113, which increases the likelihood of electron/hole recombination in the depletion region 118. Consequently, the width variations generated by the masked dopant implantation lead to significantly large ideality variations (≈4%) in the CMOS diodes currently available for the 90 nm node circuits, which is far beyond the desired variation limit.
There is therefore a need for an improved CMOS diode structure with reduced P/N gate variation, which function to reduce the width variation of the accumulation region and its interaction with the underlying depletion region and thereby reduce diode ideality variation.
There is further a need for a simple and cost-effective method for fabricating the improved CMOS diode structure that is compatible with conventional CMOS fabrication process, with few or no additional processing steps.